1. Field of the Invention
The present invention relates generally to multi-chip modules and, more specifically, to multi-chip modules that include semiconductor devices in stacked arrangement. In particular, the present invention relates to multi-chip modules that include at least one semiconductor device with a spacer predisposed on a surface thereof and another semiconductor device in stacked relation thereto and spaced vertically apart therefrom by way of the predisposed spacer. More particularly, the predisposed spacer may be printed onto a surface of the at least one semiconductor device.
2. Background of Related Art
In order to conserve the amount of surface area, or “real estate,” consumed on a carrier substrate, such as a circuit board, by semiconductor devices connected thereto, various types of increased-density packages have been developed. Among these various types of packages is the so-called “multi-chip module” (MCM). Some types of multi-chip modules include assemblies of semiconductor devices that are stacked one on top of another. The amount of space on a carrier substrate that may be saved by stacking semiconductor devices is readily apparent—a stack of semiconductor devices consumes roughly the same amount of real estate on a carrier substrate as a single, horizontally oriented semiconductor device or semiconductor device package.
Due to the disparity in processes that are used to form different types of semiconductor devices (e.g., the number and order of various process steps), the incorporation of different types of functionality into a single semiconductor device has proven very difficult to actually reduce to practice. Even in cases where semiconductor devices that carry out multiple functions can be fabricated, multi-chip modules that include semiconductor devices with differing functions (e.g., memory, processing capabilities, etc.) are often much more desirable since the separate semiconductor devices may be fabricated and assembled with one another much more quickly and cost-effectively (e.g., lower production costs due to higher volumes and lower failure rates).
Multi-chip modules may also contain a number of semiconductor devices that perform the same function, effectively combining the functionality of all of the semiconductor devices thereof into a single package.
An example of a conventional, stacked multi-chip module includes a carrier substrate, a first, larger semiconductor device secured to the carrier substrate, and a second, smaller semiconductor device positioned over and secured to the first semiconductor device. The second semiconductor device does not overlie bond pads of the first semiconductor device and, thus, the second semiconductor device does not cover bond wires that electrically connect bond pads of the first semiconductor device to corresponding contacts or terminals of the carrier substrate. Accordingly, the vertical spacing between adjacent semiconductor devices and, thus, the thickness of the adhesive layer are not critical. Such a multi-chip module is disclosed and illustrated in U.S. Pat. No. 6,212,767, issued to Tandy on Apr. 10, 2001 (hereinafter “the '767 Patent”). As the sizes of the semiconductor devices of such a multi-chip module must continue to decrease as they are positioned increasingly higher on the stack, the obtainable heights of such multi-chip modules become severely limited.
Another example of a conventional multi-chip module is described in U.S. Pat. No. 5,323,060, issued to Fogal et al. on Jun. 21, 1994 (hereinafter “the '060 Patent”). The multi-chip module of the '060 patent includes a carrier substrate with semiconductor devices disposed thereon in a stacked arrangement. The individual semiconductor devices of each multi-chip module may be the same size or different sizes, with upper semiconductor devices being either smaller or larger than underlying semiconductor devices. Adjacent semiconductor devices of each of the multi-chip modules disclosed in the '060 Patent are secured to one another with an adhesive layer, such as preformed, thermoplastic tape. The thickness of each adhesive layer exceeds the loop heights of wire bonds protruding from a semiconductor device upon which that adhesive layer is to be positioned. Accordingly, the presence of each adhesive layer prevents the back side of an overlying, upper semiconductor device from contacting bond wires that protrude from an immediately underlying, lower semiconductor device of the multi-chip module. The adhesive layers of the multi-chip modules disclosed in the '060 Patent do not encapsulate or otherwise cover any portion of the bond wires that protrude from any of the lower semiconductor devices.
A similar but more compact multi-chip module is disclosed in U.S. Pat. Re. 36,613, issued to Ball on Mar. 14, 2000 (hereinafter “the '613 Patent”). The multi-chip module of the '613 Patent includes many of the same features as those disclosed in the '060 Patent, including adhesive layers that space adjacent semiconductor devices apart a greater distance than the loop heights of wire bonds protruding from the lower of the adjacent dice. The use of thinner bond wires with low loop profile wire bonding techniques permits adjacent semiconductor devices of the multi-chip module disclosed in the '060 Patent to be positioned more closely to one another than adjacent semiconductor devices of the multi-chip modules disclosed in the '060 Patent. Nonetheless, additional space remains between the tops of the bond wires protruding from one semiconductor device and the back side of the next higher semiconductor device of such a multi-chip module.
Conventionally, stacked multi-chip modules that include semiconductor devices that overlie bond pads of the next, underlying semiconductor device include spacers, which may be formed from dielectric-coated silicon or polyimide film, to space the adjacent semiconductor devices apart from one another a sufficient distance to prevent bond wires protruding above the lower semiconductor device from contacting the back side of the upper semiconductor device. An adhesive material typically secures such a spacer between the adjacent semiconductor devices. When such spacers are used in the fabrication of multi-chip modules, each spacer must be properly aligned with and placed upon an active surface of the semiconductor device over which the spacer is to be positioned. These additional assembly processes may be somewhat undesirable for various reasons. For example, positioning of a spacer between each pair of adjacent semiconductor devices adds to assembly time. Further, additional steps in the assembly process increase the risk that semiconductor devices or discrete conductive elements may be damaged. In addition, the use of preformed spacers may undesirably add to the cost of a multi-chip module.
The vertical distance that adjacent semiconductor devices of a stacked type multi-chip module are spaced apart from one another may be reduced by arranging the immediately underlying semiconductor devices such that upper semiconductor devices are not positioned over bond pads of immediately underlying semiconductor devices or bond wires protruding therefrom. The vertical spacing of adjacent semiconductor devices in such an assembly is not critical and may be a distance that is less than the loop heights of the wire bonds that protrude above the active surface of the lower semiconductor device. U.S. Pat. No. 6,051,886, issued to Fogal et al. on Apr. 18, 2000 (hereinafter “the '886 Patent”) discloses such a multi-chip module. According to the '886 Patent, wire bonding is not conducted until all of the semiconductor devices of such a multi-chip module have been assembled with one another and with the underlying carrier substrate. The semiconductor devices of the multi-chip modules disclosed in the '886 Patent must include bond pads that are arranged on opposite peripheral edges. Semiconductor devices with bond pads positioned adjacent the entire peripheries thereof could not be used in the multi-chip modules of the '886 Patent. This is a particularly undesirable limitation due to the ever-increasing feature density of state-of-the-art semiconductor devices, which is often accompanied by a consequent need for an ever-increasing number of bond pads on semiconductor devices.
In view of the foregoing, it appears that semiconductor devices including stacking spacers formed directly on at least one side thereof would be useful, as would methods for forming such assemblies.